Conventional chip manufacturing is divided into front-end, back-end, and tail-end processing. Front-end of the line (FEOL) processing refers to the fabrication of transistors, while back-end of the line (BEOL) processing describes wafer metallization. Tail-end of the line (TEOL) processing refers to the packaging of the individual dice. Generally, the final wafer-level process step is the fabrication of vias through a passivation layer to expose the die pads, which serve as the interface between the die and the package. Each individual die, while still part of the wafer, is then functionally tested to identify known good die (KGD) followed by wafer singulation. The KGDs are then shipped to a packaging foundry where they are individually placed in a temporary package for burn-in. The dice that pass this test are then individually packaged into their final package and tested again for functionality. This final step concludes tail-end processing and the functional packaged dice are finally ready for system assembly.
The mechanical performance of a package is important for wafer-level testing, protection, and reliability. Wafer-level testing of electrical devices requires simultaneous reliable electrical contact across a surface area. Typically, neither the wafer nor the testing substrate is planar enough to enable this reliable temporary electrical contact. In-plane (i.e., x-y axis) compliance is generally required to account for potential problems such as, for example, thermal expansion between the chip and printed wiring board and probe contact with leads. Wafer-level testing and burn-in demands significant out-of-plane (i.e., z-axis) compliance in order to establish reliable electrical contact between the pads on the non-planar wafer and pads/probes on the board surfaces. Non-compliance of the input/output (I/O) interconnects/pads out-of-plane, as well as in-plane (i.e., x-y axis), can cause difficulties in performing wafer-level testing.
Unlike conventional packaging, wafer-level packaging (WLP) is a continuation of integrated circuit manufacturing. In WLP, additional masking steps can be used after BEOL processing to simultaneously package all dice across the wafer. A unique class of WLP is called compliant wafer-level packaging (CWLP). In CWLP, additional masking steps can be used following BEOL to batch fabricate compliant x-y-z axis I/O leads between the die pads and the board pads. A mechanically x-y-z flexible lead is formed between the die pad and the bump interconnection that would be joined with the board. The compliant lead allows the interconnection of chips to boards with a coefficient of thermal expansion (CTE) mismatch and, as a result, no underfill is needed. In addition, the compliant interconnect allows wafer-level functionality testing as well as wafer-level burn-in to identify known good packaged die (KGPD). WLP allows the semiconductor industry to extend the economic benefits of wafer-level processing to chip I/O interconnection (i.e., cheaper packaging).
The surface area of a WLP is exactly equal to the area of a die, and thus, the net area available for the design/fabrication of x-y-z-compliant leads is predefined. Thus, it is important to develop a lead design that allows very high compliance and high I/O density. The cost, size, weight, and performance of electronic packages significantly influence the overall cost, weight, size, and performance of electronic systems.
Accordingly, there is a need in the industry for x-y-z compliant leads that provide high density, high electrical performance, low cost, and the ability of batch fabrication. Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.